1. Field of the Invention
The invention is directed to a method for controlling the allocation of a memory access that a plurality of active units of an assembly, particularly at least one microprocessor and at least one input/output unit, request.
2. Description of the Related Art
Controller assemblies are utilized in current communication systems for control purposes, their architecture comprising a central bus, according to the known von Neumann Architecture shown in FIG. 1, which is accessed in common by the units present in the assembly.
By way of example, FIG. 1 shows a central BUS to which a microprocessor CPU, two of a plurality of possible, active input/output units AE1, AE2 and two of a plurality of possible, passive input/output units PE1, PE2 are connected. Furthermore, a memory unit SP is directly connected to the bus and, at the same time, via a preceding control unit ST. Such an active input/output unit such as an ATM protocol module, has its own controller that actively sends control signals, addresses and/or data to the shared memory or receives them from the shared memory. In contrast to this, the exchange of control signals, addresses and/or data between passive input/output units and the shared memory is controlled via the microprocessor. Such a passive input/output unit can, for example, be a serial V.24 interface that, for example, serves for the connection of an operating terminal.
In order to control the allocation of a memory access between a plurality of active units of an assembly, i.e., for example, a microprocessor CPU and an input/output unit AE2, the previously used method is shown in a flow chart in FIG. 2.
By using vertical lines, FIG. 2 indicates the active units CPU and AE2, the control unit ST, an allocation function ZF integrated in the control unit and the shared memory SP. The time direction of the method is viewed from top to bottom.
In the example illustrated in FIG. 2, the active unit CPU requests the memory access from the allocation function with a request command REQ1. The allocation function grants the active unit CPU memory access ZG1 to the memory. The active units CPU can now direct a command sequence to the memory. The active unit AE2 now requests memory access from the allocation function with a request command REQ2. At approximately the same time, the control unit ST delivers the last command PRECHARGE1 of the command sequence sent from the active unit CPU in the direction of the control unit to the memory. So that the allocation function can now allocate the memory access to the active unit AE2, it switches the active unit CPU inactive with respect to the memory access on the basis of a hold signal. Before the active unit CPU can send an acknowledged signal ACK to the allocation function, the data D1 requested by the previously deposited command sequence must have arrived at the active unit CPU, these data D1 are only capable of being sent from the memory delayed after the arrival of the command sequence. After reception of the acknowledgment signal ACK, the allocation function can assign the memory access ZG2 to the memory SP to the active unit AE2. The active unit AE2 now delivers a command sequence to the memory, after which it receives the requested data D2 after a delay time. This method is disadvantageous insofar as, for a change of the allocation of the memory access, a time loss of at least one clock arises. In the example, at least one clock after the acknowledgment signal ACK up to the allocation of the memory access ZG2 to the memory to the active unit AE2 is not used. On the controller assembly, the microprocessor and the active input/output units constantly access the shared memory, so that the time loss when changing the allocation to the memory access critically influences the performance of the controller assembly.
Additionally, for a frequent change of the allocation of the memory access, the fundamentally present pipeline-like structure of the memory cannot be utilized, i.e., that successive command cycles can be implemented with a time overlap. This disadvantage is particularly illustrated by FIG. 3.
FIG. 3 shows a pipeline processing of the control unit ST. When the memory access is currently allocated to the active unit CPU, the active unit CPU delivers a command sequence B1 to the memory within a memory access cycle. One command of the command sequence is executed per clock of the memory access cycle. FIG. 3 shows such a command sequence having, for example, six commands 11 through 16. A datum of the data sequence D1 that is referenced 21 through 26 and that corresponds to a command is received by the control unit with an at least one-clock delay after implementation of the command. It is also shown that an allocation of the memory access to the active unit AE2 can only ensue after the acknowledgment signal ACK of the active unit CPU. Accordingly, the command sequence 31 through 36 of the active unit AE2 can only be executed one clock after allocation of the memory access. The corresponding case as for the data sequence D1 having the data 21 through 26 applies to the data sequence D2 having the data 41 through 46.
As presented in FIG. 3, the pipeline-like structure of the control unit, which serves for fast command execution, cannot be utilized. Additionally, as mentioned above, a time loss always arises with every change of the allocation of the memory access, since the memory access cycle of the first active unit, for example CPU, must be ended, the allocation of the memory access must then be given to the second active unit, for example AE2, and only then can the second active unit start the memory access cycle.
Due to these disadvantages, the performance capability of such a controller assembly is critically deteriorated.
A similar architecture is shown in FIG. 1 of European Patent Application EP 0 321 628 A1. Given this architecture, the xe2x80x9cmemory user devicesxe2x80x9d 1 and 2 comprise shared control, address and data bus lines leading to the xe2x80x9cmemory controllerxe2x80x9d. In order to enable a pipeline processing of the commands directed to the memory, specific, separate control, address and data lines are additionally present between the respective xe2x80x9cuser devicexe2x80x9d and the xe2x80x9cmemory controllerxe2x80x9d unit. One disadvantage in this architecture is that, when processing the command sequence directed to the memory, a blockage-free address or data stream on the shared control, address or data bus lines must remain in consideration so that an optimization of the processing of the command sequence has limits placed on it.
The object of the invention is to provide a method for controlling the allocation of a memory access to the effect that a further performance enhancement of an assembly described above can be achieved.
This object is achieved by a method for controlling an allocation of a memory access that a plurality of active units of an assembly request, comprising the steps of withdrawing the memory access, by an allocation function within a control unit that controls communications and the data exchange between such active units respectively connected to such a control unit via a bus interface and a memory connected to the control unit via a bus interface, from an active unit to which the memory access is currently allocated; allocating the memory access to another active unit requesting a memory access no later than a point in time at which a last command of a current memory access cycle is directed to the memory by the control unit connected to the memory; and receiving, by each active unit, a message from the control unit with respect to the last command of the current memory access cycle directed to the memory.
The principle underlying the invention is comprised in advancing the point in time in which an allocation function integrated in a central control unit withdraws such a memory access from an active unit to which the memory access is currently allocated and assigns it to another active unit requesting the memory access. This is done to the extent that the last command of the current memory access cycle has already been delivered to the memory by the control unit connected to the memory and every active unit has received a message with respect to the last command of the current memory access cycle directed to the memory. The inventive method, however, assumes an arrangement of the units on an assembly in such a way that at least one central control unit controls the communication and the data exchange between such active units respectively connected to a control unit via a bus interface and a memory connected to a control unit. Such active units are, in particular, at least one microprocessor and at least one input/output unit.
Due to the fact that the change of the allocation of memory access is already initiated no later than at the point in time of the last command directed to the memory, what is achieved is that the memory access smoothly switches from one active unit to another without time losses.
According to an advantageous development of the invention, the active unit from which the currently allocated memory access is allowed to be withdrawn sends a corresponding message to a control unit at that point in time after a message with respect to the last command of the current memory access cycle directed to the memory has arrived at it. What is thus achieved is that it is not only the control unit that decides by itself above the allocation of memory access but that additional information from the active units can enter into the decision of the control unit.
According to another development of the invention, all requests of the active units for allocation of the memory access are stored in a control unit, and the subsequently allocation of the memory access is successively received by the requesting, active units.
The allocation of a memory access to the requesting active units can also be implemented according to the priority of the request in conformity with a development of the invention.
By storing all requests of the active units and the sequence of the allocation of the memory access, the control unit is supported in the pipeline processing of memory accesses, i.e., successive memory access cycles are implemented with a time overlap.
A next development of the invention provides that a memory access cycle be ended in that an active unit to which the memory access has been allocated at the beginning of the memory access cycle receives an individual message for the reception of data from the memory. This favors the situation thatxe2x80x94when the control unit has directed the last command to the memoryxe2x80x94the allocation function can already assign the memory access to another active unit before the active unit to which the memory access was most recently allocated has the requested data available to it. At that point in time in which the data are available, the active unit therefore receives an individual message for the reception of the data from the memory. In other words, such a message is individually directed to the active unit requesting the data. The data thus arrive at the active unit that previously requested the data even though the active unit may potentially already have had the memory access withdrawn from it.